1. Field of the Invention
The present invention generally relates to pipeline-operation devices, and particularly relates to a memory device carrying out pipeline operations.
2. Description of the Prior Art
As a foundation of an information society, DRAM (dynamic random access memory) chips are widely used because of their capacity to allow integrated circuits to be manufactured in high density. In order to boost speed of data-read/write operations, DRAMs are typically provided with various functions contrived for the purpose of speed enhancement, an example of such functions being a page mode. With an aim of achieving high-speed data transfer, also, SDRAM (synchronous DRAM) is-created as a variation of DRAMs to carry out data-read/write operations in synchronism with a clock-signal.
FIGS. 1A and 1B are time charts showing a data-read timing of a conventional DRAM operating in the page mode. FIGS. 1C through 1E are time charts showing a data-read timing of an SDRAM operating in a burst mode.
In the DRAM page mode as shown in FIG. 1A, a plurality of column addresses CA1, CA2, CA3, and CA4 are provided during a single cycle between an input of a given row address RA1 and an input of a next row address RA2. As shown in FIG. 1B, four pieces of data Q1, Q2, Q3, and Q4 in this case can be read out at 20-nanoseconds (ns) for example, as long as these pieces of data are stored in the same row address. When data is stored in consecutive addresses or in the same row address, use of the page mode is highly effective.
In the SDRAM burst mode as shown in FIG. 1D, a first column address CA1 is provided in synchronism with a clock signal CLK (FIG. 1C) during one cycle between an input of a given row address RA1 and an input of a next row address RA2, and column addresses following the first column address CA1 are internally generated in the memory chip. As shown in FIG. 1E, data pieces Q1, Q2, Q3, and Q4 are continuously read from the memory at high speed in synchronism with the clock signal CLK, as long as these data pieces are stored in the same row address. Similar to the requirements of the DRAM page mode, the SDRAM burst mode achieves a high-speed-data-read operation only when data addresses are continuous or have the same row address.
The DRAM page mode of FIG. 1A and the SDRAM burst-mode of FIG. 1D have the same cycle period between successive row-address inputs as that of DRAMs operating in the normal mode. Because of this, the use of the SDRAM or the DRAM page mode can achieve only a data-read speed as fast as that of the normal mode when the data-read addresses are random rather than in the same row address.
DRAMs require a sequence of operations to be conducted within one cycle period between successive row accesses, such sequence including precharging bit-lines (column addresses) to get the bit-lines ready, selecting a word-line (row address) to transfer data to a sense amplifier, and selecting a bit-line to read the data. Because of such a long sequence, the cycle of the row accesses becomes as much as about 100 ns. In other words, since DRAMs require the precharging of bit-lines prior to each data-read operation, consecutive data-read operations are difficult to achieve when read-data addresses are random.
In order to overcome this difficulty, a memory may be divided into a plurality of banks. In principle, this is the same as providing a plurality of memory chips of the same type. With N banks provided, random data access should end up accessing a bank different from the one accessed immediately before at a probability of (Nxe2x88x921)/N. Each bank other than the bank accessed immediately before is already precharged and ready, so that consecutive data-read/write operations can be achieved by accessing different banks one after another.
In such a memory-bank method, however, each bank should be provided with a dedicated set of control circuits while only one of such a set is normally required for a whole memory device. This means that an increase in the bank number leads to an enlargement in the chip size.
Accordingly, there is a need for a memory device which allows address accesses to be consecutively made at high speed by providing a plurality of memory blocks capable of identical operations without enlarging the chip size.
Accordingly, it is a general object of the present invention to provide a memory device which can satisfy the need described above.
It is another and more specific object of the present invention to provide a memory device which allows address accesses to be consecutively made at high speed by providing a plurality of memory blocks capable of identical operations without enlarging the chip size.
In order to achieve the above objects, a device according to the present invention includes a plurality of blocks, each being capable of carrying out different types of operations, and a control unit for selecting one block after another from the plurality of blocks. In this device, each selected block upon a selection thereof starts carrying out the operations in a predetermined order in a pipe-line operation such that every one of the operations is in progress in one of the blocks at a given time. Here, the terminology xe2x80x9cblockxe2x80x9d represents a core circuit having an array of repeated structures, an example of which is an array of cells sharing a set of sense amplifiers in DRAMs. Alternately, such a block is a unit of repetition in terms of a layout such as a set of several cell-array blocks, or is a bank in terms of an address logic.
In the device described above, the control unit for selecting a block is shared by the plurality of blocks so that there is no need to provide a complex controlling mechanism for each of the blocks. In addition, while a given block is carrying out a given operation, another block which has already finished this given operation can carry out a next operation following the given operation. In this manner, the blocks as a whole perform predetermined operations in a pipe-line manner, thereby achieving high-speed processing.
According to one embodiment of the present invention, each block includes a unit for selecting one operation after another so as to carry out the operations in the predetermined order. Because of this feature, the control unit only selects one block after another to achieve the pipe-line operation.
According to another embodiment of the present invention, the control unit includes a unit for selecting one operation after another in the predetermined order and for instructing each selected block at every turn to carry out a selected one of the operations. Because of this feature, each block only performs an instructed operation to achieve the pipe-line operation.
According to one embodiment of the present invention, the control unit includes a unit for detecting a disturbance in the pipe-line operation so that each selected block delays carrying out the operations. Because of this feature, even when the pipe-line operation is disturbed, all the required operations can be carried out without skipping any one of the operations.
According to one embodiment of the present invention, the control unit includes a unit for detecting a disturbance in the pipe-line operation so that each selected block skips one of the operations causing this disturbance and carries out following ones of the operations. Because of this feature, even when there is a cause to create a disturbance in the pipe-line operation, an operation causing the disturbance is skipped to achieve a smooth pipe-line operation.
According to one embodiment of the present invention, the control unit includes a unit for outputting a signal indicating a detection of a disturbance via the input/output unit. Because of this feature, the control unit can signal the disturbance when an instruction resulting in the disturbance of the pipe-line operation is provided.
According to one embodiment of the present invention, the device is provided with various functions to enhance an input and output interface, such functions including demultiplexing a signal input and multiplexing a signal output based on a supplied strobe signal. Because of these functions, the input and output interface makes an efficient use of a limited number of input/output pins while enhancing the data-output performance.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.